document number: 91175 www.vishay.com s09-0516-rev. c, 13-apr-09 1 power mosfet irfib6n60a, sihfib6n60a vishay siliconix features ? low gate charge q g results in simple drive requirement ? improved gate, avalanche and dynamic dv/dt ruggedness ? fully characterized capacitance and avalanche voltage and current ? compliant to rohs directive 2002/95/ec applications ? switch mode power supply (smps) ? uninterruptible power supply ? high speed power switching ? high voltage isolation = 2.5 kv rms (t = 60 s, f = 60 hz) typical smps topologies ? single transistor forward ? active clamped forward notes a. repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. starting t j = 25 c, l = 6.8 mh, r g = 25 , i as = 9.2 a (see fig. 12). c. i sd 9.2 a, di/dt 50 a/s, v dd v ds , t j 150 c. d. 1.6 mm from case. product summary v ds (v) 600 r ds(on) ( )v gs = 10 v 0.75 q g (max.) (nc) 49 q gs (nc) 13 q gd (nc) 20 configuration single n -channel mosfet g d s s d g to-220 fullpak a v aila b le rohs* compliant ordering information package to-220 fullpak lead (pb)-free IRFIB6N60APBF sihfib6n60a-e3 snpb irfib6n60a sihfib6n60a absolute maximum ratings t c = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds 600 v gate-source voltage v gs 30 continuous drain current v gs at 10 v t c = 25 c i d 5.5 t c = 100 c 3.5 pulsed drain current a i dm 37 linear derating factor 0.48 w/c single pulse avalanche energy b e as 290 mj repetitive avalanche current a i ar 9.2 a repetitive avalanche energy a e ar 6.0 mj maximum power dissipation t c = 25 c p d 60 w peak diode recovery dv/dt c dv/dt 5.0 v/ns operating junction and storage temperature range t j , t stg - 55 to + 150 c soldering recommendations (p eak temperature) for 10 s 300 d mounting torque 6-32 or m3 screw 10 lbf in 1.1 n m * pb containing terminations are not rohs compliant, exemptions may apply
www.vishay.com document number: 91175 2 s09-0516-rev. c, 13-apr-09 irfib6n60a, sihfib6n60a vishay siliconix notes a. repetitive rating; pulse width limited by maximum junction temper ature (see fig. 11). b. pulse width 300 s; duty cycle 2 %. c. c oss eff. is a fixed capacitance that gi ves the same charging time as c oss while v ds is rising from 0 % to 80 % v ds . d. t = 60 s, f = 60 hz. thermal resistance ratings parameter symbol typ. max. unit maximum junction-to-ambient r thja -65 c/w maximum junction-to-case (drain) r thjc -2.1 specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 600 - - v v ds temperature coefficient v ds /t j reference to 25 c, i d = 1 ma d - 660 - mv/c gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 2.0 - 4.0 v gate-source leakage i gss v gs = 30 v - - 100 na zero gate voltage drain current i dss v ds = 600 v, v gs = 0 v - - 25 a v ds = 480 v, v gs = 0 v, t j = 125 c - - 250 drain-source on-state resistance r ds(on) v gs = 10 v i d = 3.3 a b - - 0.75 forward transconductance g fs v ds = 25 v, i d = 5.5 a 5.5 - - s dynamic input capacitance c iss v gs = 0 v, v ds = 25 v, f = 1.0 mhz, see fig. 5 - 1400 - pf output capacitance c oss - 180 - reverse transfer capacitance c rss -7.1- output capacitance c oss v gs = 0 v v ds = 1.0 v, f = 1.0 mhz - 1957 - v ds = 480 v, f = 1.0 mhz - 49 - effective output capacitance c oss eff. v ds = 0 v to 480 v c -96- total gate charge q g v gs = 10 v i d = 9.2 a, v ds = 400 v, see fig. 6 and 13 b --49 nc gate-source charge q gs --13 gate-drain charge q gd --20 turn-on delay time t d(on) v dd = 300 v, i d = 9.2 a, r g = 9.1 , r d = 35.5 , see fig. 10 b -13- ns rise time t r -25- turn-off delay time t d(off) -30- fall time t f -22- drain-source body diode characteristics continuous source-drain diode current i s mosfet symbol showing the integral reverse p - n junction diode --5.5 a pulsed diode forward current a i sm --37 body diode voltage v sd t j = 25 c, i s = 9.2 a, v gs = 0 v b --1.5v body diode reverse recovery time t rr t j = 25 c, i f = 9.2 a, di/dt = 100 a/s b - 530 800 ns body diode reverse recovery charge q rr -3.04.4c forward turn-on time t on intrinsic turn-on time is neglig ible (turn-on is dominated by l s and l d ) s d g
document number: 91175 www.vishay.com s09-0516-rev. c, 13-apr-09 3 irfib6n60a, sihfib6n60a vishay siliconix typical characteristics 25 c, unless otherwise noted fig. 1 - typical output characteristics fig. 2 - typical output characteristics fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature 0.1 1 10 100 0.1 1 10 100 20 s pulse w idth t = 25 c j top bottom v gs 15 v 10 v 8 .0 v 7.0 v 6.0 v 5.5 v 5.0 v 4.7 v v , drain-to-so u rce v oltage ( v ) i , drain-to-so u rce c u rrent (a) ds d 4.7 v 1 10 100 1 10 100 20 s pulse w idth t = 150 c j top bottom v gs 15 v 10 v 8 .0 v 7.0 v 6.0 v 5.5 v 5.0 v 4.7 v v , drain-to-so u rce v oltage ( v ) i , drain-to-so u rce c u rrent (a) ds d 4.7 v 0.1 1 10 100 4.0 5.0 6.0 7.0 8 .0 9.0 10.0 v = 50 v 20 s pulse w idth ds v , gate-to-so u rce v oltage ( v ) i , drain-to-so u rce c u rrent (a) gs d t = 25 c j t = 150 c j -60 -40 -20 0 20 40 60 8 0 100 120 140 160 0.0 0.5 1.0 1.5 2.0 2.5 3.0 t , j u nction temperat u re ( c) r , drain-to-so u rce on resistance ( n ormalized) j ds(on) v = i = gs d 10 v 9.2a
www.vishay.com document number: 91175 4 s09-0516-rev. c, 13-apr-09 irfib6n60a, sihfib6n60a vishay siliconix fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage fig. 7 - typical source-drain diode forward voltage fig. 8 - maximum safe operating area 0 400 8 00 1200 1600 2000 2400 1 10 100 1000 c, capacitance (pf) ds v , drain-to-so u rce v oltage ( v ) a v = 0 v , f = 1mhz c = c + c , c shorted c = c c = c + c gs iss gs gd ds rss gd oss ds gd iss oss rss 0 10 20 30 40 50 0 4 8 12 16 20 q , total gate charge (nc) v , gate-to-so u rce v oltage ( v ) g gs for test circuit see figure i = d 13 9.2a v = 120 v ds v = 300 v ds v = 4 8 0 v ds 0.1 1 10 100 0.2 0.5 0.7 1.0 1.2 v ,so u rce-to-drain v oltage ( v ) i , re v erse drain c u rrent (a) sd sd v = 0 v gs t = 25 c j t = 150 c j 0.1 1 10 100 1000 10 100 1000 10000 operatio n i n this area limited by r ds(on) single p u lse t t = 150 c = 25 c j c v , drain-to-so u rce v oltage ( v ) i , drain c u rrent (a) i , drain c u rrent (a) ds d 10 u s 100 u s 1ms 10ms
document number: 91175 www.vishay.com s09-0516-rev. c, 13-apr-09 5 irfib6n60a, sihfib6n60a vishay siliconix fig. 9 - maximum drain current vs. case temperature fig. 10a - switching time test circuit fig. 10b - switching time waveforms fig. 11 - maximum effective transient thermal impedance, junction-to-case fig. 12a - unclamped inductive test circuit fig. 12b - unclamped inductive waveforms 25 50 75 100 125 150 0.0 1.0 2.0 3.0 4.0 5.0 6.0 t , case temperat u re ( c) i , drain c u rrent (a) c d v ds p u lse w idth 1 s d u ty factor 0.1 % r d v gs r g d.u.t. 10 v + - v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 10 n otes: 1. d u ty factor d = t / t 2. peak t = p x z + t 1 2 j dm thjc c p t t dm 1 2 t , rectang u lar p u lse d u ration (s) thermal response (z ) 1 thjc 0.01 0.02 0.05 0.10 0.20 d = 0.50 si n gle pulse (thermal respo n se) a r g i as 0.01 t p d.u.t. l v ds + - v dd dri v er a 15 v 20 v t p v ds i as
www.vishay.com document number: 91175 6 s09-0516-rev. c, 13-apr-09 irfib6n60a, sihfib6n60a vishay siliconix fig. 12c - maximum avalanche energy vs. drain current fig. 13a - basic gate charge waveform fig. 13b - gate charge test circuit 25 50 75 100 125 150 0 100 200 300 400 500 600 starting t , j u nction temperat u re ( c) e , single p u lse a v alanche energy (mj) j as i d top bottom 4.1a 5. 8 a 9.2a q g q gs q gd v g charge 10 v d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v c u rrent reg u lator c u rrent sampling resistors same type as d.u.t. + -
document number: 91175 www.vishay.com s09-0516-rev. c, 13-apr-09 7 irfib6n60a, sihfib6n60a vishay siliconix fig. 14 - for n-channel vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91175 . p. w . period di/dt diode reco v ery d v /dt ripple 5 % body diode for w ard drop re-applied v oltage re v erse reco v ery c u rrent body diode for w ard c u rrent v gs = 10 v * v dd i sd dri v er gate dri v e d.u.t. i sd w a v eform d.u.t. v ds w a v eform ind u ctor c u rrent d = p. w . period + - + + + - - - * v gs = 5 v for logic le v el de v ices peak diode recovery dv/dt test circuit r g v dd ? d v /dt controlled b y r g ? dri v er same type as d.u.t. ? i sd controlled b y d u ty factor "d" ? d.u.t. - de v ice u nder test d.u.t. circ u it layo u t considerations ? lo w stray ind u ctance ? gro u nd plane ? lo w leakage ind u ctance c u rrent transformer
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